1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device, a semiconductor device, a stacked semiconductor device, a circuit board, and an electronic instrument.
2. Related Art
In recent years, in portable electronic instruments such as portable telephones, notebook type personal computers, and PDAs (Personal Digital Assistants), there have been designs to miniaturize the various kinds of electronic parts such as semiconductor devices, which are provided therein, to satisfy the demands for miniaturization and light weight. Against such a background, a three dimensional mounting technique for semiconductors is proposed. This three dimensional mounting technique is a technique for stacking semiconductor devices having similar functions, or semiconductor devices having different functions.
Furthermore, small size and thin semiconductors are desirable for mounting in three dimensions. Therefore, in Japanese Unexamined Patent Application, First Publication No. 2001-127206, as a method of manufacturing a thin semiconductor device, there is disclosed a method of manufacturing a semiconductor device in which, after forming a plurality of semiconductor devices for example on a semiconductor wafer, and after thinning by back grinding, the semiconductor wafer is cut by dicing to separate the semiconductor devices into individual pieces.
Incidentally, cracks, in what is known as a subsurface damaged layer, are formed in the surface of a semiconductor wafer processed by back grinding. These cracks are prone to be starting points of cracks in the semiconductor wafer, thus they reduce the transverse strength of the semiconductor wafer itself. Moreover, chips and cracks occur on the side wall sections of semiconductor chips formed by cutting the semiconductor wafer by dicing. Therefore, the semiconductor chips can get broken easily, with the chips and cracks being starting points, thus the strength of a semiconductor device itself provided with the semiconductor chips is reduced. Furthermore, the edges of the semiconductor chips cut by dicing are substantially verticalness. In this case, stress concentration occurs at the edges, so that cracks and chips are generated easily on the thin semiconductor chips. Therefore, there is a problem in that the strength of the semiconductor device is reduced.